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november 2007 rev 5 1/20 1 M48Z02 m48z12 5v, 16kbit (2kb x 8) zeropower ? sram features integrated, ultra low power sram and power- fail control circuit unlimited write cycles read cycle time equals write cycle time automatic power-fail chip deselect and write protection write protect voltages (v pfd = power-fail dese lect voltage): ?M48Z02: v cc = 4.75 to 5.5v; 4.5v v pfd 4.75v ?m48z12: v cc = 4.5 to 5.5v; 4.2v v pfd 4.5v self-contained batter y in the caphat? dip package pin and function compatible with jedec standard 2k x 8 srams rohs compliant ? lead-free second level interconnect 24 1 pcdip24 (pc) battery caphat? www.st.com
contents M48Z02, m48z12 2/20 contents 1 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M48Z02, m48z12 list of tables 3/20 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 10. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. pcdip24 ? 24-pin plastic dip, battery caph at?, package mechanical data . . . . . . . . . 17 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
list of figures M48Z02, m48z12 4/20 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. write enable controlled, write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. checking the bok flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. pcdip24 ? 24-pin plastic dip, battery caphat?, package outline . . . . . . . . . . . . . . . . . 17
M48Z02, m48z12 summary 5/20 1 summary the M48Z02/12 zeropower ? ram is a 2k x 8 non-volatile static ram which is pin and functional compatible with the ds1220. a special 24-pin, 600mil dip caphat? package houses the M48Z02/12 silicon with a long life lithium button cell to form a highly integrated battery backed-up memory solution. the M48Z02/12 button cell has sufficient capacity and storage life to maintain data functionality for an accumulated time period of at least 10 years in the absence of power over commercial operating temperature range. the M48Z02/12 is a non-volatile pin and function equivalent to any jedec standard 2k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special wr ite timing or limitations on the number of writes that can be performed. figure 1. logic diagram table 1. signal names a0-a10 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground ai01186 11 a0-a10 w dq0-dq7 v cc M48Z02 m48z12 g v ss 8 e
summary M48Z02, m48z12 6/20 figure 2. dip connections figure 3. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 a10 a8 a9 dq7 w g e dq5 dq1 dq2 dq3 v ss dq4 dq6 v cc ai01187 M48Z02 m48z12 8 1 2 3 4 5 6 7 9 10 11 12 16 15 24 23 22 21 20 19 18 17 14 13 ai01255 lithium cell v pfd v cc v ss voltage sense and switching circuitry 2k x 8 sram array a0-a10 dq0-dq7 e w g power
M48Z02, m48z12 operation modes 7/20 2 operation modes the M48Z02/12 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc . as v cc falls below approximately 3v, the control circuitry connects the battery which maintains data operation until valid power returns. table 2. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 2.1 read mode the M48Z02/12 is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. thus, the unique address specified by the 11 address inputs defines which one of the 2,048 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activated before t avqv , the data lines will be driven to an indete rminate state until t avqv . if the address inputs are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. mode v cc e g w dq0- dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) 1. see table 10 on page 16 for details. x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
operation modes M48Z02, m48z12 8/20 figure 4. read mode ac waveforms note: write enable (w ) = high. table 3. read mode ac characteristics 2.2 write mode the M48Z02/12 is in the write mode whenever w and e are active. the start of a write is referenced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70c or ?40 to 85c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). M48Z02/m48z12 unit ?70 ?150 ?200 min max min max min max t avav read cycle time 70 150 200 ns t avqv address valid to output valid 70 150 200 ns t elqv chip enable low to output valid 70 150 200 ns t glqv output enable low to output valid 35 75 80 ns t elqx chip enable low to output transition 5 10 10 ns t glqx output enable low to output transition 5 5 5 ns t ehqz chip enable high to output hi-z 25 35 40 ns t ghqz output enable high to output hi-z 25 35 40 ns t axqx address transition to output transition 10 5 5 ns ai01330 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a10 e g dq0-dq7 valid
M48Z02, m48z12 operation modes 9/20 figure 5. write enable controlled, write ac waveform figure 6. chip enable controlled, write ac waveforms ai01331 tavav twhax tdvwh data input a0-a10 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01332b tavav tehax tdveh a0-a10 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
operation modes M48Z02, m48z12 10/20 table 4. write mode ac characteristics 2.3 data retention mode with valid v cc applied, the M48Z02/12 operates as a conventional bytewide? static ram. should the supply voltage decay, the ra m will automatically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as ?don't care.? note: a power failure during a write cycle may corr upt data at the curren tly addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the M48Z02/12 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recommended. the power switching circuit connects external v cc to the ram and disconnects the battery when v cc rises above v so . as v cc rises, the battery voltage is checked. if the voltage is too low, an internal battery not ok (bok ) flag will be set. the bok flag can be checked after power up. if the bok flag is set, the first write attemp ted will be blocked. the flag is automatically cleared after the first write, and normal ram operation resumes. figure 7 on page 11 illustrates how a bok check routine could be structured. for more information on a battery storage life refer to the application note an1012. symbol parameter (1)(1) 1. valid for ambient operating temperature: t a = 0 to 70c or ?40 to 85c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). M48Z02/m48z12 unit ?70 ?150 ?200 min max min max min max t avav write cycle time 70 150 200 ns t avwl address valid to write enable low 0 0 0 ns t avel address valid to chip enable 1 low 0 0 0 ns t wlwh write enable pulse width 50 90 120 ns t eleh chip enable low to chip enable 1 high 55 90 120 ns t whax write enable high to address transition 0 10 10 ns t ehax chip enable high to address transition 0 10 10 ns t dvwh input valid to write enable high 30 40 60 ns t dveh input valid to chip enable high 30 40 60 ns t whdx write enable high to input transition 5 5 5 ns t ehdx chip enable high to input transition 5 5 5 ns t wlqz write enable low to output hi-z 25 50 60 ns t avwh address valid to write enable high 60 120 140 ns t aveh address valid to chip enable high 60 120 140 ns t whqx write enable high to output transition 5 10 10 ns
M48Z02, m48z12 operation modes 11/20 figure 7. checking the bok flag status 2.4 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low goin g spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1f (as shown in figure 8 on page 12 ) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, stmicroelectronics recommends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. read data at any address ai00607 is data complement of first read? (battery ok) power-up yes no write data complement back to same address read data at same address again notify system of low battery (data may be corrupted) write original data back to same address (battery low) continue
operation modes M48Z02, m48z12 12/20 figure 8. supply voltage protection ai02169 v cc 0.1 f device v cc v ss
M48Z02, m48z12 maximum rating 13/20 3 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 5. absolute maximum ratings caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c t stg storage temperature (v cc off, oscillator off) ?40 to 85 c t sld (1) 1. soldering temperature not to exceed 260c for 10 se conds (total thermal budget not to exceed 150c for longer than 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
dc and ac parameters M48Z02, m48z12 14/20 4 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in ta b l e 6 : operating and ac measurement conditions . designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 6. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 9. ac testing load circuit table 7. capacitance parameter M48Z02 m48z12 unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 v ambient operating temperature (t a ) grade 1 0 to 70 0 to 70 c load capacitance (c l ) 100 100 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v symbol parameter (1)(2) 1. effective capacitance measured with power supply at 5v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. min max unit c in input capacitance 10 pf c io (3) 3. outputs deselected. input / output capacitance 10 pf ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k device under test 1k
M48Z02, m48z12 dc and ac parameters 15/20 table 8. dc characteristics figure 10. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e high as v cc rises past v pfd (min). some systems may perform inadvertent write cycles after v cc rises above v pfd (min) but before normal system operati ons begin. even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running. symbol parameter test condition (1) 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). min max unit i li input leakage current 0v v in v cc 1 a i lo (2) 2. outputs deselected. output leakage current 0v v out v cc 1 a i cc supply current outputs open 80 ma i cc1 supply current (standby) ttl e = v ih 3ma i cc2 supply current (standby) cmos e = v cc ? 0.2v 3 ma v il input low voltage ?0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = ?1ma 2.4 v ai00606 v cc inputs (per control input) outputs don't care high-z tf tfb tr trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so
dc and ac parameters M48Z02, m48z12 16/20 table 9. power down/up ac characteristics table 10. power down/up trip points dc characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). min max unit t pd e or w at v ih before power down 0 s t f (2) 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write prot ection not occurring until 200s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 0 s t rb v ss to v pfd (min) v cc rise time 1 s t rec e or w at v ih after power up 2 ms symbol parameter (1)(2) 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). min typ max unit v pfd power-fail deselect voltage M48Z02 4.5 4.6 4.75 v m48z12 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr (3) 3. at 25c, v cc = 0v. expected data retention time 10 years
M48Z02, m48z12 package mechanical data 17/20 5 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 11. pcdip24 ? 24-pin plastic dip, battery caphat?, package outline note: drawing is not to scale. table 11. pcdip24 ? 24-pin plastic dip, battery caphat?, package mechanical data pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 34.29 34.80 1.350 1.370 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 25.15 30.73 0.990 1.210 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n24 24
part numbering M48Z02, m48z12 18/20 6 part numbering table 12. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. example: m48z 02 ?70 pc 1 device type m48z supply voltage and write protect voltage 02 = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 12 = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v speed ?70 = 70ns (M48Z02/12) ?150 = 150ns (M48Z02/12) ?200 = 200ns (M48Z02/12) package pc = pcdip24 temperature range 1 = 0 to 70c shipping method blank = ecopack package, tubes
M48Z02, m48z12 revision history 19/20 7 revision history table 13. document revision history date revision changes may-1999 1.0 first issue 09-jul-2001 2.0 reformatted; temperature information added to tables ( ta b l e 5 , 6 , 7 , 8 , 3 , 4 , 9 , 10 ); figure updated ( figure 10 ) 17-dec-2001 2.1 remove referenc es to ?clock? in document 20-may-2002 2.2 updated v cc noise and negative going transients text 01-apr-2003 3.0 v2.2 template applied; test condition updated ( ta b l e 1 0 ) 22-apr-2003 3.1 fix error in ordering information ( ta bl e 1 2 ) 12-dec-2005 4.0 update template, lead-free text, and remove references to ?crystal? and footnote ( ta bl e 8 , 12 ) 02-nov-2007 5 reformatted document; added lead-f ree second level interconnect information to cover page and section 5: package mechanical data ; updated ta b l e 5 , 6 , 8 , 9 , 10 , 12 .
M48Z02, m48z12 20/20 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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